VHDL, meet Mr. Mallet

So, here I am sitting in the dank submarine hole (aka RCH, the engineering building that's 2/3rds underground), waiting for time to pass so I can get this lab over and done with. VHDL isn't playing nice, though I guess that's mostly due to design flaws. Redesigning and then reprogramming is going to be painful >_<. My partner and I are contemplating doing the lab as a schematic instead... lol. Schematics are incredibly messy though... or at least the one we first tried putting together was =P. But they seem to make a lot more sense than all this random "port map"-ing

In other news! Ummm ::thinks:: Oh, Kingston. Maybe. Depending on whether this lab gets done or not. I haven't seen Amanda/JC/Jacob in ages, so I'd rather not have to bail out (oh, you too Robert =P).

Just came out of an interview 30 min ago. I think it went well =). I doubt I'll get the job though, since there are probably plenty of other applicants who are far more competant than I in networking and such.

Well, time to go home and make lunch (mmmm, pork ribs) :D
... and then rush off to finish up this lab business